The present invention relates generally to flip chip technology and more particularly, to a method and structure for reducing internal packaging stresses, improving adhesion properties, and reducing thermal resistance in flip chip packages by using more than one underfill material deposited in specific patterns.
The packaging industry has adopted the widespread use of flip chip technology for high performance applications. In a typical flip chip package, a semiconductor die may be bumped with individual conducting pads over its entire area. These conducting pads are connected to corresponding conducting pads on a substrate (or, in a three-dimensional package, another semiconductor die or interposer) using small solder balls, or bumps, such as controlled collapse chip connections (C4 connections). The conducting pads on the substrate may be connected to circuitry that routes the electrical signals to an array of conductors (ball grid arrays (BGA), column grid arrays (CGA) or land grid arrays (LGA)) to electrically connect to a printed circuit board.
Open spaces commonly remain between the C4 connections in the flip chip interface of the semiconductor die and the substrate. These open spaces may be filled with a non-conductive adhesive “underfill” material to protect the bumps and the flip chip interface from moisture, contaminants, and other environmental hazards. More importantly, this underfill material mechanically locks the flip chip surface to the substrate, thereby reducing the strains imposed on the small bumps due to the difference between the coefficient of thermal expansion (CTE) of the flip chip and the substrate. The underfill consequently prevents the bumps from being damaged (e.g., cracking, severing) during thermal expansion of the module.